Huawei to Launch 960DT and Ascend 960PR AI Chips in 2027

David Wang fixed the dates. At the Huawei company summit that opened in Shanghai on Thursday, the rotating chairman told that two new artificial-intelligence chips would reach the market the following year.

The 960DT would launch in the first quarter of 2027. The Ascend 960PR would follow in the third. The event ran three days, from September 17 through 19. Wang, also known as Wang Tao, delivered the schedule in the city.

More than 1,000 supernodes have already shipped to more than 370 customers. A supernode is a linked system that brings many AI chips together to tackle the same task. What holds those chips in step is UnifiedBus, Huawei’s interconnect technology for joining AI processors into larger systems so they share information and operate as one computing unit rather than a set of isolated parts.

Most advanced AI programs need more processing power than any single chip can supply. Linking chips only works when the path between them keeps pace with the workload; UnifiedBus is built for that exchange. Eleven semiconductors have been developed on the technology for use in the company’s large systems. Huawei’s AI chip ecosystem has 5,270 monthly active developers, the base the company points to when it talks about making the processors practical for the people who write the models.

Earlier in September, Guo Ping stood before Huawei’s new hires at an internal company meeting and set the terms of the work ahead.

“We are closing the gap by innovating chip architectures,” Guo said. Architecture, in this sense, means the internal layout of a chip and the way it is wired to memory, networking, and the software that runs on top of it. He reached outside the semiconductor industry for the example he wanted them to carry. “Apple was not a leader in making processors at the beginning, but they delivered exceptional user experience through architecture redesigns and software optimization.”

The goal he gave the room was plain: Huawei’s chips should be able to operate every AI model, in China and beyond. Raw single-chip speed was not the whole measure. The path ran through how the silicon was arranged, how the software sat on it, and how those two layers were tuned together.

At Mobile World Congress in Barcelona in March 2026, Huawei demonstrated a rack of 64 neural processing units, or NPUs. An NPU is a chip specialized for the matrix math that AI models run. The same configuration scaled to 8,192 chips. That packaging is the Atlas 950 SuperPoD, built around the Ascend 950DT.

The 950DT is slated for release in the fourth quarter of 2026. It carries 144GB of memory. Memory bandwidth—the speed at which data moves between the processor and its memory—runs at 4TB per second. Interconnect bandwidth—the speed at which chips exchange data so they can work as one computer—runs at 2TB per second. Filled to capacity, the SuperPoD links up to 8,192 Ascend 950DT chips.

The linked system reaches 8 exaFLOPS of FP8 compute. An exaFLOPS is a quintillion floating-point operations every second. FP8 is the eight-bit floating-point format that many large AI models use for training and inference.

Morgan Stanley analyst Charlie Chan laid out the market view in a recent research note.

“System-level competitiveness matters more than ever,” Chan said.

“The effective gap is narrowing through multi-die design, advanced packaging, rack-scale system architecture, optical networking, and software-hardware co-optimization,” he wrote. Multi-die design builds a processor from several pieces of silicon sealed inside one package so they act as a single larger unit. Advanced packaging is the assembly technique that bonds those dies and the connections between them tightly enough for high-speed data to pass without bottleneck. Rack-scale system architecture treats a full rack of processors as one computer rather than a collection of separate boards. Optical networking moves information as light instead of electricity, reducing delay when chips sit farther apart. Software-hardware co-optimization means rewriting programs and reshaping chip layouts together so each side covers what the other cannot do alone.

On September 4, seven Chinese government agencies issued a policy document calling for 800V high-voltage DC power delivery and for racks exceeding 100kW. High-voltage direct current at 800 volts supplies computing cabinets with steady DC rather than ordinary building AC, and at a voltage high enough that large wattage reaches each rack without extreme current in the cables. Lower current for the same power cuts heat lost in the conductors and the bulk of copper required to carry the load. A rack that exceeds 100 kilowatts packs the draw of processors, memory, and interconnect into a single cabinet far denser than a standard server frame.

Those two thresholds—800 volts on the feed and more than 100 kilowatts per rack—set the physical floor for the halls meant to hold the next generation of linked systems. Without power delivery that can keep pace, the advantage of joining large numbers of chips stops at the wall.

Huawei superclusters can support up to 1 million AI processors.